1. Field of the Invention
The present invention generally relates to integrated scanning systems for reading multiple insignia impregnated on a surface of different articles and, more particularly, to scanning system based on nano-components and integrated in one monolithic device.
2. Description of Related Art
A general concept of a scanning device has been discussed in a number of U.S. patents and publications. Multiple scanning devices currently are available on a market for reading various insignia impregnated on a surface. On the other hand, the progress in the nanotechnology and particular in the manufacturing of resonantly excited scanning mirrors, light emitting and receiving components, and micro optics have reached a point when it have become apparent that new concepts for the design of compact monolithic micro scanners should be applied.
The challenge of designing of integrated scanning devices had evolved over the years as the scale and extend of functions assigned to devices has increased. The integration requirements have evolved in much the same way. As the scale and extend increased, the single function system became less practical. Multifunctional system design presented a new set of problems related to physical, electrical, logical, and etc. system interactions. Collaboration between different components/modules/subsystems carrying out application tasks usually requires a sharing of signals and/or data. Designers typically are solving these collaboration problems by employing specific proprietary schemes.
For a long time the focus in the system design was on a chip level, making chips smaller, faster, more powerful and more efficient while simultaneously reducing cost and improving reliability. The manufacturers simply designed the integrated circuits and packaged them. There have been several fundamental shifts in the history of electronic packaging that profoundly affected an electronic industry, such as                Surface mount technology (SMT)        Area array packages, like ball grid array (BGA)        Chip scale packaging        Wafer level packaging (WLP)        
From a functional point of view, a package is a link between the small dimensions of the integrated circuits and the larger dimensions of the printed circuit boards. It is quite obvious that methods developed for integrated microelectronic assembly could be applied for integrating and packaging more complex monolithic systems with multiple physical components. A monolithic micro scanner is expected to have several advantages compared with conventional scanners: smaller physical footprint, less power consumption, and longer lifetime.
A crucial objective of nanotechnology is to make products inexpensively. Inherently nanotechnology is suitable for low-cost production and high flexibility in production, which is vital for maintaining continuous competitive capability for any technology.
The design of smaller, lighter, and thinner scanning system is only possible by further miniaturization of system's components and implementation of the conceptually new design architecture. System on a package (SOP) paradigm provides such desired capabilities.
SOP offers significant savings in space and costs, as well as provides an optimum distribution of functions between or within system's components. There are several advantages of SOPs compare to other integrating technologies:                SOPs can carry diverse components form factors such as flip chips, SMT discretes, etc.        It is based on techniques and know-how developed for maximum utilization of the surface area of the package; it also relaxing the application board design requirements.        Low package failure rates can be achieved through the use of different techniques and proven board attachment technologies.        Electrical characteristics and efficiency are enhanced through shorter interconnections of die on an SOP.        SOP is shortening a design time. Use of SOP can eliminate the need to design a single, large, complex chip to contain diverse functions. Smaller, functional chips can be tightly integrated into an SOP, often with no sacrifice in layout complexity vs. a single chip solution.        
The integration of MEMS scanning systems fundamentally has close association with particular applications. There is a significant difference between the rationales for packaging integrated circuits (IC) and packaging MEMS based scanning devices. The purpose of IC packaging is to provide physical support for the chip, to provide an electrical interface to active chips in the system, to supply signal, power and ground interconnections, allow heat dissipation, and to isolate the chip physically from its environment. MEMS devices, on the other hand, are intended to interface directly with their environment. Consequently, they need an application specific packaging scheme and a corresponding functional interface. MEMS's package is a part of a complete system and all components of the system must function together and be compatible with each other.
Numerous approaches for designing integrated scanning systems are known in the prior art. However, their main focus was on the integration of a scanning device on a common substrate. It is a purpose of the present invention to provide a monolithic scanning device, which can be composed from multiple components with different form factors, utilizes with high efficiency available package space to provide “more functionality in a smaller space”, and has a superior performance.